Mod-03 Lec-03 Two level Boolean Logic Synthesis-3 Free Video Tutorials and Notes Lectures
Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT Guwahati. For more details on NPTEL visit http://nptel.iitm.ac.in